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INTEGRATED CIRCUITS
DATA SHEET
LPC2106/LPC2105/LPC2104 Single-chip 32-bit microcontrollers
128kB ISP/IAP FLASH with 64kB/32kB/16kB RAM
Objective Specification 2003 Apr 10
Philips Semiconductors
PHILIPS
Philips Semiconductors
Data Sheet
CMOS single-chip 32-bit microcontroller TABLE OF CONTENTS
LPC2104/2105/2106
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 On-Chip Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 On-Chip static RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Pin Connect Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Function Select Register 0 (PINSEL0 - 0xE002C000) . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose Parallel I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 UARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 I2C Serial I/O Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 SPI Serial I/O Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 General Purpose Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Real Time Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pulse Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Reset & Wakeup Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 External Interrupt Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Memory Mapping Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VPB Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Emulation and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Embedded ICE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Embedded Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 RealMonitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Data Sheet
CMOS single-chip 32-bit microcontroller GENERAL DESCRIPTION
LPC2104/2105/2106
The LPC 2104, 2105 and 2106 consist of an ARM7TDMI-S CPU with emulation support, the ARM7 Local Bus for interface to onchip memory controllers, the AMBA Advanced High-performance Bus (AHB) for interface to the interrupt controller, and the VLSI Peripheral Bus (VPB, a compatible superset of ARM's AMBA Advanced Peripheral Bus) for connection to on-chip peripheral functions.
Features
* ARM7TDMI-S processor. * 128 kilobyte on-chip Flash Program Memory with In-System Programming (ISP) and In-Application Programming (IAP) capability. Flash programming time is 1 ms for up to a 512 byte line. Sector erase or chip erase is done in 400 ms. * Up to 64 kilobyte Static RAM. * Vectored Interrupt Controller. * Emulation Trace Module supports real-time trace. * Standard ARM Test/Debug interface for compatibility with existing tools. * Two UARTs, one with full modem interface. * Fast I2C serial interface (400kb/s). * SPI serial interface. * Two timers, each with 4 capture/compare channels. * PWM unit with up to 6 PWM outputs. * Real Time Clock. * Watchdog Timer. * General purpose I/O pins. * CPU operating range up to 60 MHz. * Dual power supply. - CPU operating voltage range of 1.65V to 1.95V (1.8V +/- 8.3%). - I/O power supply range of 3.0V to 3.6V (3.3V +/- 10%). * Two low power modes, Idle and Power Down. * Processor wakeup from Power Down mode via external interrupt. * Individual enable/disable of peripheral functions for power optimization. * On-chip crystal oscillator with an operating range of 10 MHz to 25 MHz. * On-chip PLL allows CPU operation up to the maximum CPU rate. May be used over the entire crystal operating range.
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Data Sheet
CMOS single-chip 32-bit microcontroller ORDERING INFORMATION
Memory Part Number Flash LPC2104BBD48 LPC2105FBD48 LPC2106BBD48 128kB 128kB 128kB RAM 16kB 32kB 64kB 0 to +70, LQFP 0 to +70, LQFP 0 to +70, LQFP Temperature Range (C) and Package
LPC2104/2105/2106
Drawing Number SOT313-2 SOT313-2 SOT313-2
PIN CONFIGURATION
46 P0.16 / EINT0 / MAT0.2 37 P0.12 / DSR1 / MAT1.0 36 P0.11 / CTS1 / CAP1.1 35 P0.10 / RTS1 / CAP1.0 34 P0.24 / PIPESTAT1 33 P0.23 / PIPESTAT0 32 P0.22 / TRACECLK 31 Vss3 30 P0.9 / RxD1 / PWM6 29 P0.8 / TxD1 / PWM4 28 P0.7 / SSEL / PWM2 27 DBGSEL 26 RTCK 25 NC P0.0 / TxD0 / PWM1 13 P0.1 / RxD0 / PWM3 14 P0.30 / TRACEPKT3 / TDI 15 P0.31 / EXTIN0 / TDO 16 Vdd3-2 (I/O) 17 P0.2 / SCL / CAP0.0 18 Vss2 19 NC 20 P0.3 / SDA / MAT0.0 21 P0.4 / SCK / CAP0.1 22 P0.5 / MISO / MAT0.1 23 P0.6 / MOSI / CAP0.2 24 41 P0.13 / DTR1 / MAT1.1 47 P0.17 / CAP1.2 / TRST 48 P0.18 / CAP1.3 / TMS 44 P0.14 / DCD1 / EINT1 39 P0.26 / TRACESYNC 38 P0.25 / PIPESTAT2 45 P0.15 / RI1 / EINT2
P0.19 / MAT1.2 / TCK P0.20 / MAT1.3 / TDI P0.21 / PWM5 / TDO NC Vdd1.8 (core) RST Vss1 P0.27 / TRACEPKT0 / TRST P0.28 / TRACEPKT1 / TMS
1 2 3 4 5 6 7 8 9
P0.29 / TRACEPKT2 / TCK 10 X1 11 X2 12
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4
40 Vdd3-1 (I/O)
43 Vss4
42 NC
Philips Semiconductors
Data Sheet
CMOS single-chip 32-bit microcontroller BLOCK DIAGRAM
LPC2104/2105/2106
TRST1
TMS1
TDO1
TCK1
TDI1
Xtal1
Xtal2
RST
Vdd
Emulation Trace Module
Test/Debug Interface
PLL
System Clock
ARM7TDMI-S
AHB Bridge
System Functions
Vectored Interrupt Controller
ARM7 Local Bus
AMBA AHB (Advanced High-performance Bus)
Internal SRAM Controller
Internal Flash Controller
AHB Decoder AHB to VPB VPB Bridge Divider VPB (VLSI Peripheral Bus)
64/32/16 kB SRAM
128 kB FLASH
EINT0 * EINT1 * EINT2 *
External Interrupts Capture / Compare Timer 0 Capture / Compare Timer 1 General Purpose I/O
I2C Serial Interface
SCL * SDA *
CAP0..2 * MAT0..2 *
SPI Serial Interface
SCK * MOSI * MISO * SSEL * TxD *
CAP0..3 * MAT0..3 *
UART0
RxD *
GPIO (32 pins)
UART1
TxD * RxD * Modem Control (6 pins) *
PWM1..6 *
PWM0
Watchdog Timer
Real Time Clock
System Control
* Shared with GPIO 1 When Test/Debug Interface is used, GPIO/other functions sharing these pins are not available
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Vss
Philips Semiconductors
Data Sheet
CMOS single-chip 32-bit microcontroller PIN DESCRIPTION
Pin Name P0.0 to P0.31 13 LQFP 48 Type Pin # I/O O O I O I/O I I/O O I/O I I/O 23 O I/O 24 I 28 I O O O I O O I I I I O O O P0.7 CAP0.2 SSEL PWM2 TxD1 PWM4 RxD1 PWM6 RTS1 CAP1.0 CTS1 CAP1.1 DSR1 MAT1.0 DTR1 MAT1.1 P0.6 MAT0.1 MOSI Description
LPC2104/2105/2106
Port 0: Port 0 is a 32-bit bi-directional I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the Pin Connect Block. P0.0 TxD0 PWM1 RxD0 PWM3 SCL CAP0.0 SDA MAT0.0 SCK CAP0.1 MISO Transmitter output for UART 0. Pulse Width Modulator output 1. Receiver input for UART 0. Pulse Width Modulator output 3. I2C clock input/output. Open drain output (for I2C compliance). Capture input for Timer 0, channel 0. I2C data input/output. Open drain output (for I2C compliance). Match output for Timer 0, channel 0. Serial Clock. SPI clock output from master or input to slave. Capture input for Timer 0, channel 1. Master In Slave Out. Data input to SPI master or data output from SPI slave. Match output for Timer 0, channel 1. Master Out Slave In. Data output from SPI master or data input to SPI slave. Capture input for Timer 0, channel 2. Slave Select. Selects the SPI interface as a slave. Pulse Width Modulator output 2. Transmitter output for UART 1. Pulse Width Modulator output 4. Receiver input for UART 1. Pulse Width Modulator output 6. Request to Send output for UART 1. Capture input for Timer 1, channel 0. Clear to Send input for UART 1. Capture input for Timer 1, channel 1. Data Set Ready input for UART 1. Match output for Timer 1, channel 0. Data Terminal Ready output for UART 1. Match output for Timer 1, channel 1.
14
P0.1
18
P0.2
21
P0.3
22
P0.4
P0.5
29
P0.8
30
P0.9
35
P0.10
36
P0.11
37
P0.12
41
P0.13
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Data Sheet
CMOS single-chip 32-bit microcontroller
Pin Name LQFP 48 Type Pin # 44 I I I I I O I I I I O I O I O O O O O O O O I O I O I O I I O P0.14 DCD1 EINT1 RI1 EINT2 EINT0 MAT0.2 CAP1.2 TRST CAP1.3 TMS MAT1.2 TCK MAT1.3 TDI PWM5 TDO
LPC2104/2105/2106
Description Data Carrier Detect input for UART 1. External interrupt 1 input. Ring Indicator input for UART 1. External interrupt 2 input. External interrupt 0 input. Match output for Timer 0, channel 2. Capture input for Timer 1, channel 2. Test Reset for JTAG interface, primary JTAG pin group. Capture input for Timer 1, channel 3. Test Mode Select for JTAG interface, primary JTAG pin group. Match output for Timer 1, channel 2. Test Clock for JTAG interface, primary JTAG pin group. Match output for Timer 1, channel 3. Test Data In for JTAG interface, primary JTAG pin group. Pulse Width Modulator output 5. Test Data Out for JTAG interface, primary JTAG pin group.
45
P0.15
46
P0.16
47
P0.17
48
P0.18
1
P0.19
2
P0.20
3 32 33 34 38 39 8
P0.21
P0.22 P0.23 P0.24 P0.25 P0.26 P0.27
TRACECLK Trace Clock. Standard I/O port with internal pullup. PIPESTAT0 Pipeline Status, bit 0. Standard I/O port with internal pullup. PIPESTAT1 Pipeline Status, bit 1. Standard I/O port with internal pullup. PIPESTAT2 Pipeline Status, bit 2. Standard I/O port with internal pullup. TRACESYNCTrace Synchronization Standard I/O port with internal pullup. TRACEPKT0Trace Packet, bit 0. Standard I/O port with internal pullup. TRST Test Reset for JTAG interface, secondary JTAG pin group. TRACEPKT1Trace Packet, bit 1. Standard I/O port with internal pullup. TMS Test Mode Select for JTAG interface, secondary JTAG pin group. TRACEPKT2Trace Packet, bit 2. Standard I/O port with internal pullup. TCK Test Clock for JTAG interface, secondary JTAG pin group. TRACEPKT3Trace Packet, bit 3. Standard I/O port with internal pullup. TDI Test Data In for JTAG interface, secondary JTAG pin group. EXTIN0 TDO External Trigger Input. Standard I/O port with internal pullup. Test Data Out for JTAG interface, secondary JTAG pin group.
9
P0.28
10
P0.29
P0.30
15 16
P0.31
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Data Sheet
CMOS single-chip 32-bit microcontroller
Pin Name RTCK LQFP 48 Type Pin # 26 I/O
LPC2104/2105/2106
Description Returned Test Clock output. Extra signal added to the JTAG port. Assists debugger synchronization when processor frequency varies. Also used during debug mode entry to select primary or secondary JTAG pins with the 48-pin package. Bi-directional pin with internal pullup. Debug Select. When low, the part operates normally. When high, debug mode is entered. Input pin with internal pulldown. External Reset input. A low on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Ground: 0V reference. 1.8V Core Power Supply: This is the power supply voltage for internal circuitry. 3.3V Pad Power Supply: This is the power supply voltage for the I/O ports. Not Connected: These pins are not connected in the 48 pin package.
DBGSEL RST X1 X2 VSS VDD1.8 VDD3 NC
27 6 11 12 7, 19, 31, 43 5 17, 40 4, 20, 25, 42
I I I O I I I -
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Data Sheet
CMOS single-chip 32-bit microcontroller FUNCTIONAL DESCRIPTION
LPC2104/2105/2106
Details of LPC2104, LPC2105 and LPC2106 systems and peripheral functions are described in the following sections.
Architectural Overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind THUMB is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: * The standard 32-bit ARM set. * A 16-bit THUMB set. The THUMB set's 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM's performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because THUMB code operates on the same 32-bit register set as ARM code. THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16-bit memory system.
On-Chip Flash Program Memory
The LPC2104, LPC2105 and LPC2106 incorporate a 128K byte Flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be accomplished in several ways. It may be programmed In System via the serial port. The application program may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.
On-Chip static RAM
On-Chip static RAM memory may be used for code and/or data storage. The SRAM may be accessed as 8-bits, 16-bits, and 32bits. The LPC2106 provides a 64K byte static RAM, the LPC2105 provides a 32K byte static RAM while the LPC2104 provides a 16K byte static RAM.
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Data Sheet
CMOS single-chip 32-bit microcontroller
Memory Map
LPC2104/2105/2106
The LPC2106, LPC2105 and LPC2104 memory maps incorporate several distinct regions, as shown in the following figures. In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either Flash memory (the default) or on-chip static RAM. This is described in the System Control section.
4.0 GB AHB Peripherals 3.75 GB VPB Peripherals 3.5 GB
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
3.0 GB Reserved Address Space
0xC000 0000
2.0 GB
Boot Block (re-mapped from On-Chip Flash memory)
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
Reserved Address Space
1.0 GB
64K Byte On-Chip Static RAM
0x4001 0000 0x4000 FFFF 0x4000 0000 0x3FFF 8000
Reserved Address Space
128K Byte On-Chip Flash Memory 0.0 GB
0x0002 0000 0x0001 FFFF 0x0000 0000
Figure 1: LPC2106 Memory Map
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Data Sheet
CMOS single-chip 32-bit microcontroller
LPC2104/2105/2106
4.0 GB AHB Peripherals 3.75 GB VPB Peripherals 3.5 GB
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
3.0 GB Reserved Address Space
0xC000 0000
2.0 GB
Boot Block (re-mapped from On-Chip Flash memory)
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
Reserved Address Space
1.0 GB
32K Byte On-Chip Static RAM
0x4000 8000 0x4000 7FFF 0x4000 0000 0x3FFF 8000
Reserved Address Space
128K Byte On-Chip Flash Memory 0.0 GB
0x0002 0000 0x0001 FFFF 0x0000 0000
Figure 2: LPC2105 Memory Map
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Data Sheet
CMOS single-chip 32-bit microcontroller
LPC2104/2105/2106
4.0 GB AHB Peripherals 3.75 GB VPB Peripherals 3.5 GB
0xFFFF FFFF 0xF000 0000 0xEFFF FFFF 0xE000 0000 0xDFFF FFFF
3.0 GB Reserved Address Space
0xC000 0000
2.0 GB
Boot Block (re-mapped from On-Chip Flash memory)
0x8000 0000 0x7FFF FFFF 0x7FFF E000 0x7FFF DFFF
Reserved Address Space
1.0 GB
16K Byte On-Chip Static RAM
0x4001 0000 0x4000 3FFF 0x4000 0000 0x3FFF 8000
Reserved Address Space
128K Byte On-Chip Flash Memory 0.0 GB
0x0002 0000 0x0001 FFFF 0x0000 0000
Figure 3: LPC2104 Memory Map
Interrupt Controller
The Vectored Interrupt Controller (VIC) accepts all of the interrupt request inputs and categorizes, them as FIQ, vectored IRQ, and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. Fast Interrupt reQuest (FIQ) has the highest priority. If more than one request is assigned to FIQ, the VIC combines the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned
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Data Sheet
CMOS single-chip 32-bit microcontroller
LPC2104/2105/2106
to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots, among which slot 0 has the highest priority and slot 15 has the lowest. Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the VIC provides the address of the highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see what IRQs are active. Interrupt Sources The following table lists the interrupt sources for each peripheral function. Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller, but may have several internal interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
Block WDT ARM Core ARM Core Timer 0 Timer 1 Watchdog Interrupt (WDINT)
Flag(s)
VIC Channel # 0 1 2 3 4 5
Reserved for software interrupts only Embedded ICE, DbgCommRx Embedded ICE, DbgCommTx Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3) Match 0 - 3 (MR0, MR1, MR2, MR3) Capture 0 - 3 (CR0, CR1, CR2, CR3) Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Rx Line Status (RLS) Transmit Holding Register empty (THRE) Rx Data Available (RDA) Character Time-out Indicator (CTI) Modem Status Interrupt (MSI) Match 0 - 6 (MR0, MR1, MR2, MR3, MR4, MR5, MR6) Capture 0 - 3 (CR0, CR1, CR2, CR3) SI (state change) SPIF, MODF reserved PLL Lock (PLOCK)
UART 0
6
UART 1
7
PWM0 I2C SPI PLL
8 9 10 11 12
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Data Sheet
CMOS single-chip 32-bit microcontroller
Block RTC System Control System Control System Control Flag(s) RTCCIF (Counter Increment), RTCALF (Alarm) External Interrupt 0 (EINT0) External Interrupt 1 (EINT1) External Interrupt 2 (EINT2)
LPC2104/2105/2106
VIC Channel # 13 14 15 16
Pin Connect Block
The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. The Pin Control Module contains 2 registers as shown below. Address 0xE002C000 0xE002C004 Name PINSEL0 PINSEL1 Pin function select register 0 Pin function select register 1 Description Access Read/Write Read/Write
Pin Function Select Register 0 (PINSEL0 - 0xE002C000)
The PINSEL0 register controls the functions of the pins as per the settings listed in Table 1. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions, direction is controlled automatically.Settings other than those shown in the table are reserved, and should not be used. PINSEL0 Pin Name 0 1:0 P0.0 0 1 0 3:2 P0.1 0 1 0 5:4 P0.2 0 1 0 7:6 P0.3 0 1 0 9:8 P0.4 0 1 Value 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 GPIO Port 0.0 TxD (UART 0) PWM1 GPIO Port 0.1 RxD (UART 0) PWM3 GPIO Port 0.2 SCL (I2C) Capture 0.0 (Timer 0) GPIO Port 0.3 SDA (I2C) Match 0.0 (Timer 0) GPIO Port 0.4 SCK (SPI) Capture 0.1 (Timer 0) 0 0 0 0 0 Function Value after Reset
Table 1: Pin Function Select Register 0 (PINSEL0 - 0xE002C000)
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Philips Semiconductors
Data Sheet
CMOS single-chip 32-bit microcontroller
PINSEL0 Pin Name 0 11:10 P0.5 0 1 0 13:12 P0.6 0 1 0 15:14 P0.7 0 1 0 17:16 P0.8 0 1 0 19:18 P0.9 0 1 0 21:20 P0.10 0 1 0 23:22 P0.11 0 1 0 25:24 P0.12 0 1 0 27:26 P0.13 0 1 0 29:28 P0.14 0 1 0 31:30 P0.15 0 1 Value 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 GPIO Port 0.5 MISO (SPI) Match 0.1 (Timer 0) GPIO Port 0.6 MOSI (SPI) Capture 0.2 (Timer 0) GPIO Port 0.7 SSEL (SPI) PWM2 GPIO Port 0.8 TxD UART 1 PWM4 GPIO Port 0.9 RxD (UART 1) PWM6 GPIO Port 0.10 RTS (UART1) Capture 1.0 (Timer 1) GPIO Port 0.11 CTS (UART1) Capture 1.1 (Timer 1) GPIO Port 0.12 DSR (UART1) Match 1.0 (Timer 1) GPIO Port 0.13 DTR (UART 1) Match 1.1 (Timer 1) GPIO Port 0.14 CD (UART 1) EINT1 GPIO Port 0.15 RI (UART1) EINT2 Function
LPC2104/2105/2106
Value after Reset
0
0
0
0
0
0
0
0
0
0
0
Table 1: Pin Function Select Register 0 (PINSEL0 - 0xE002C000)
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Philips Semiconductors
Data Sheet
CMOS single-chip 32-bit microcontroller
Pin Function Select Register 1 (PINSEL1 - 0xE002C004)
LPC2104/2105/2106
The PINSEL1 register controls the functions of the pins as per the settings listed in Table 2. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. Function control for the pins P0.17 - P0.31 is effective only when the DBGSEL input is pulled LOW during RESET. PINSEL1 Pin Name 0 1:0 P0.16 0 1 3:2 5:4 7:6 9:8 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 P0.17 P0.18 P0.19 P0.20 P0.21 P0.22 P0.23 P0.24 P0.25 P0.26 P0.27 P0.28 P0.29 P0.30 P0.31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Value 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 GPIO Port 0.16 EINT0 Match 0.2 (Timer 0) GPIO Port 0.17 Capture 1.2 (Timer 1) GPIO Port 0.18 Capture 1.3 (Timer 1) GPIO Port 0.19 Match 1.2 (Timer 1) GPIO Port 0.20 Match 1.3 (Timer 1) GPIO Port 0.21 PWM5 GPIO Port 0.22 GPIO Port 0.23 GPIO Port 0.24 GPIO Port 0.25 GPIO Port 0.26 GPIO Port 0.27 TRST GPIO Port 0.28 TMS GPIO Port 0.29 TCK GPIO Port 0.30 TDI GPIO Port 0.31 TDO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Value after Reset
Table 2: Pin Function Select Register 1 (PINSEL1 - 0xE002C004)
General Purpose Parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back, as well as the current state of the port pins.
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Data Sheet
CMOS single-chip 32-bit microcontroller
Features * Direction control of individual bits. * Separate control of output set and clear. * All I/O default to inputs after reset.
LPC2104/2105/2106
UARTs
The LPC2104, LPC2105 and LPC2106 each contain two UARTs. One UART provides a full modem control handshake interface, the other provides only transmit and receive data lines. Features * 16 byte Receive and Transmit FIFOs. * Register locations conform to `550 industry standard. * Receiver FIFO trigger points at 1, 4, 8, and 14 bytes. * Built-in baud rate generator. * Standard modem interface signals included on UART 1.
I2C Serial I/O Controller
I2C is a bi-directional bus for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. I2C is a multi-master bus, it can be controlled by more than one bus master connected to it. I2C implemented in LPC2104, LPC2105 and LPC2106 supports bit rate up to 400 kbit/s (Fast I2C). Features * Standard I2C compliant bus interface. * Easy to configure as Master, Slave, or Master/Slave. * Programmable clocks allow versatile rate control. * Bidirectional data transfer between masters and slaves. * Multi-master bus (no central master). * Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. * Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. * Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. * The I2C bus may be used for test and diagnostic purposes.
SPI Serial I/O Controller
The SPI is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends a byte of data to the slave, and the slave always sends a byte of data to the master. Features * Compliant with Serial Peripheral Interface (SPI) specification.
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Data Sheet
CMOS single-chip 32-bit microcontroller
* Synchronous, Serial, Full Duplex, Communication. * Combined SPI master and slave. * Maximum data bit rate of one eighth of the input clock rate.
LPC2104/2105/2106
General Purpose Timers
The Timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions at specified timer values, based on four match registers. It also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. Features * A 32-bit Timer/Counter with a programmable 32-bit Prescaler. * Up to four (TImer 1) and three (Timer 0) 32-bit capture channels, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. * Four 32-bit match registers that allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Up to four (Timer 1) and three (Timer 0) external outputs corresponding to match registers, with the following capabilities: - Set low on match. - Set high on match. - Toggle on match. - Do nothing on match.
Watchdog Timer
The purpose of the Watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the Watchdog will generate a system reset if the user program fails to "feed" (or reload) the Watchdog within a predetermined amount of time. Features * Internally resets chip if not periodically reloaded * Debug mode * Enabled by software but requires a hardware reset or a Watchdog reset/interrupt to be disabled * Incorrect/Incomplete feed sequence causes reset/interrupt if enabled * Flag to indicate Watchdog reset * Programmable 32-bit timer with internal pre-scaler * Selectable time period from (t pclk x 256 x 4) to (t pclk x 2 32 x 4) in multiples of t pclk x 4
Real Time Clock
The Real Time Clock (RTC) is designed to provide a set of counters to measure time during system power on and off operation. The RTC has been designed to use little power, making it suitable for battery powered systems where the CPU is not running continuously (Idle mode).
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Data Sheet
CMOS single-chip 32-bit microcontroller
Features * Measures the passage of time to maintain a calendar and clock. * Ultra Low Power design to support battery powered systems.
LPC2104/2105/2106
* Provides Seconds, Minutes, Hours, Day Of Month, Month, Year, Day of Week, and Day of Year. * Programmable Reference Clock Divider allows adjustment of the RTC to match various crystal frequencies.
Pulse Width Modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2104, LPC2105 and LPC2106. The Timer is designed to count cycles of the peripheral clock (pclk) and optionally generate interrupts or perform other actions when specified timer values occur, based on seven match registers. It also includes four capture inputs to save the timer value when an input signal transitions, and optionally generate an interrupt when those events occur. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (MR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the MR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). Features * Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. * The match registers also allow: - Continuous operation with optional interrupt generation on match. - Stop timer on match with optional interrupt generation. - Reset timer on match with optional interrupt generation. * Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. * Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. * Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. * Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must "release" new match values before they can become effective. * May be used as a standard timer if the PWM mode is not enabled. * A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
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Data Sheet
CMOS single-chip 32-bit microcontroller
System Control
Crystal Oscillator
LPC2104/2105/2106
The oscillator supports crystals in the range of 10 MHz to 25 MHz. The oscillator output frequency is called FOSC and the ARM processor clock frequency is referred to as cclk for purposes of rate equations, etc. FOSC and cclk are the same value unless the PLL is running and connected. Refer to the PLL description for additional information. PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency. The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2, it is insured that the PLL output has a 50% duty cycle.The PLL is turned off and bypassed following a chip Reset and may be enabled by software. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. Reset & Wakeup Timer Reset has two sources on the LPC2104, LPC2105 and LPC2106: the RST pin and Watchdog Reset. The RST pin is a Schmitt trigger input pin with an additional glitch filter. Assertion of chip Reset by any source starts the Wakeup Timer (see Wakeup Timer description below), causing the internal chip reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip Flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is the Reset vector. At that point, all of the processor and peripheral registers have been initialized to predetermined values. The wakeup timer ensures that the oscillator and other analog functions required for chip operation are fully functional before the processor is allowed to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power Down mode, any wakeup of the processor from Power Down mode makes use of the Wakeup Timer. The Wakeup Timer monitors the crystal oscillator as the means of checking whether it is safe to begin code execution. When power is applied to the chip, or some event caused the chip to exit Power down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of Vdd ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. External Interrupt Inputs The LPC2104, LPC2105 and LPC2106 include three External Interrupt Inputs as selectable pin functions. The External Interrupt Inputs can optionally be used to wake up the processor from Power Down mode. Memory Mapping Control The Memory Mapping Control alters the mapping of the interrupt vectors that appear beginning at address 0x00000000. Vectors may be mapped to the bottom of the on-chip Flash memory, or to the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts.
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Data Sheet
CMOS single-chip 32-bit microcontroller
Power Control
LPC2104/2105/2106
The LPC2104, LPC2105 and LPC2106 support two reduced power modes: Idle mode and Power Down mode. In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. In Power Down mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Power Down mode and the logic levels of chip output pins remain static. The Power Down mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Power Down mode reduces chip power consumption to nearly zero. A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. VPB Bus The VPB Divider determines the relationship between the processor clock (cclk) and the clock used by peripheral devices (pclk). The VPB Divider serves two purposes. The first is that the VPB bus cannot operate at the highest speeds of the CPU. In order to compensate for this, the VPB bus may be slowed down to one half or one fourth of the processor clock rate. The default condition at reset is for the VPB bus to run at one quarter of the CPU clock. The second purpose of the VPB Divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. Because the VPB Divider is connected to the PLL output, the PLL remains active (if it was running) during Idle mode.
Emulation and Debugging
The LPC2104, LPC2105 and LPC2106 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Each of these functions requires a trade-off of debugging features versus device pins. Because the LPC2104, LPC2105 and LPC2106 are provided in a small package, there is no room for permanently assigned JTAG or Trace pins. An alternate JTAG port allows an option to debug functions assigned to the pins used by the primary JTAG port. Embedded ICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM core. The ARM core has a Debug Communication Channel function in-built. The debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The debug communication channel is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The debug communication channel allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The debug communication channel data and control registers are mapped in to addresses in the EmbeddedICE logic. Embedded Trace Since the LPC2104, LPC2105 and LPC2106 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. The Embedded Trace Macrocell provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to the trace port. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external trace port analyzer must capture the trace information under software
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Philips Semiconductors
Data Sheet
CMOS single-chip 32-bit microcontroller
LPC2104/2105/2106
debugger control. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC (Debug Communications Channel), which is present in the EmbeddedICE logic. The LPC2104, LPC2105 and LPC2106 contain a specific configuration of RealMonitor software programmed into the on-chip Flash memory.
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Data Sheet
CMOS single-chip 32-bit microcontroller ABSOLUTE MAXIMUM RATINGS
Symbol VDD1.8 VDD3 VI VI I I Tstg Parameter Supply voltage, internal rail Supply voltage, external rail DC input voltage, 5V tolerant I/O pins DC supply current per supply pin DC ground current per ground pin Storage temperature
8 7 7 5, 6
LPC2104/2105/2106
Min -0.5 -0.5 -0.5 -0.5
Max +2.5 +3.6 6.0 VDD3 + 0.5 100 100
Unit V V V V mA mA C
DC input voltage, other I/O pins 4, 5
-40 1.5 W
125
Power dissipation (based on package heat transfer, not device power consumption)
Notes: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification are not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. 4. Not to exceed 4.6 V 5. Including voltage on outputs in tri-state mode 6. Only valid when the VDD3 supply voltage is present 7. The peak current is limited to 25 times the corresponding maximum current. 8. Dependent on package type
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Data Sheet
CMOS single-chip 32-bit microcontroller DC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70C for commercial, -40C to +85C for industrial, unless otherwise specified. Symbol VDD1.8 VDD3 CIO IIL IIH IOZ Ilatchup VI VO VIH VIL Vhys VOH VOL IOH IOL IOH IOL IPD IPU Supply voltage External rail supply voltage Input/Output pin capacitance
2
LPC2104/2105/2106
Parameter
Test Conditions
LIMITS Min 1.65 3.0 Typ.1 1.8 3.3 Max 1.95 3.6 tbd
Unit V V pF A A A mA
Standard Port pins, RST, RTCK, and DBGSEL Low level input current; no pull-up High level input current; no pull down Tri-state output leakage; no pull-up/down I/O latch-up current Input voltage 3, 4, 5 Output voltage; output active High level input voltage Low level input voltage Hysteresis voltage High level output voltage 6 Low level output voltage High level output current Low level output current
6 6 6 7
VI = 0 VI = VDD3 VO = 0; VO = VDD3 -(0.5*VDD3) < V < (1.5*VDD3) Tj < 125 C 100 0 0 2.0
3 3 3
5.5 VDD3 0.8 0.4
V V V V V V
IOH = -4 mA IOL = 4 mA VOH = VDD3 - 0.4V VOL = 0.4 V VOH = 0 VOL = VDD3 Vi = 5V Vi = 0 VDD3 < Vi < 5V
8 8
VDD3 - 0.4 0.4 -4 4 -45 50 20 -25 0 50 -50 0 100 -65 0
V mA mA mA mA A A A
High level short circuit current
Low level short circuit current 7 Pull-down current (applies to DBGSEL) Pull-up current (applies to P0.22 - P0.31)
VDD1.8=1.8V, cclk=60MHz, Tamb=25C, code Active Mode IDD1.8 while(1){} executed from FLASH, no active peripherals VDD1.8=1.8V, Tamb=+25C, VDD1.8=1.8V, Tamb=+85C, VTOL is from 4.5V to 5.5V VTOL is from 4.5V to 5.5V VTOL is from 4.5V to 5.5V
6
30
mA
Power Down Mode I2C pins High level input voltage Low level input voltage Hysteresis voltage Low level output voltage
10 50 0.7 * VTOL 0.3 * VTOL 0.5 * VTOL 0.4 170
A A V V V V
VIH VIL Vhys VOL
IOL = 3 mA
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Philips Semiconductors
Data Sheet
CMOS single-chip 32-bit microcontroller
LPC2104/2105/2106
LIMITS Min Typ.1 2 10 0 0 Max 4 22 VDD1.8 VDD1.8
Symbol Ilkg
Parameter Input leakage to VSS
Test Conditions Vi = VDD3 Vi = 5V
Unit A A
Oscillator pins X1 input Voltages? X2 output Voltages?
Notes: 1. Typical ratings are not guaranteed. The values listed are for room temperature, nominal supply voltages. 2. Pin capacitance is characterized but not tested. 3. Including voltage on outputs in tri-state mode 4. VDD3 supply voltages must be present 5. Tri-state outputs go into tri-state mode when VDD3 is grounded 6. Accounts for 100mV voltage drop in all supply lines 7. Only allowed for a short time period 8. Minimum condition for Vi = 4.5V, Maximum condition for Vi = 5.5V
AC ELECTRICAL CHARACTERISTICS
Tamb = 0 to +70C for commercial, -40C to +85C for industrial, VDD1.8, VDD3 over specified ranges 1, 2 Symbol Parameter Test Conditions LIMITS Min 10 40 tC * 0.4 tC * 0.4 5 5 10 10 20 + 0.1 * Cb 3 Typ.1 Max 25 100 Unit
External Clock fC Oscillator frequency tC tCHCX tCLCX tCLCH tCHCL Oscillator clock period Clock high-time Clock low time Clock rise time Clock fall time
MHz ns ns ns ns ns ns ns
Port Pins tRISE Port output rise time (except P0.2, P0.3) tFALL I2C pins tf Output fall time from VIH to VIL Port output fall time (except P0.2, P0.3)
ns
Notes: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for all outputs = TBD pF. 3. Bus capacitance Cb in pF, from 10 pF to 400 pF
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Philips Semiconductors
Data Sheet
CMOS single-chip 32-bit microcontroller
LPC2104/2105/2106
VDD - 0.5 0.45V
0.2VDD+0.9 0.2 VDD - 0.1 tCHCX tCHCL tCLCX tC tCLCH
Figure 4: External Clock Timing
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